In electronic design automation (EDA), functional verification is the task of verifying that a logic design conforms to its specification. Logic simulation is the process of simulating a logic design before the logic design manufactured as integrated circuits (ICs). In software simulation, a description of the logic design is simulated on computers or workstations. Logic designs may be described using various languages, such as hardware description languages (HDLs) or other more abstract languages (e.g., synthesizable SystemC). In software simulation, engineers write a test-bench program to functionally verify the logic design by providing meaningful scenarios to check that, given certain input stimuli, the design performs to specification. A test-bench may be written using various languages, including lower-level languages, such as very high speed integrated circuit HDL (VHDL), Verilog, and the like, as well as more abstract languages, such as C/C++, SystemC, SystemVerilog, and the like. Higher-level languages, such as SystemC, allow engineers to write more abstract test-bench models for simulation, such as transaction-level models (TLMs), as opposed to lower-level register transfer level (RTL) models.
The test bench includes various components that may be tested. However, in certain cases, it may be difficult for the components to communicate with each other.